Towards an Integrated Framework for Reliability-Aware Embedded System Design on Multiprocessor System-on-Chips

Today’s integrated circuits are becoming more susceptible to faults due to effects caused by aggressive technology scaling. However, to meet the ever-increasing reliability requirements of safety-related applications, the system has to function correctly even in the presence of faults. This leads to the challenging problem of fault-tolerant system design. Here, the goal is to meet the required level of reliability with minimum overhead, while guaranteeing the system’s timing, resource and other constraints. This thesis presents an integrated framework tackling the problem above. The framework features modeling, analysis, optimization and code generation tools to support a complete reliability-aware design flow. Its modeling approach allows for abstract description of the application and the underlying execution platform. Using the models as input, the reliability analysis and multi-criteria optimization techniques enable automated exploration of design alternatives. Fault Tolerant Mechanisms (FTMs), including spatial/temporal redundancy, fault detection and voting are actively embedded into the design to meet the reliability goal. We extend the existing approaches by dropping inappropriate assumptions in the fault model and supporting a larger set of FTMs. Finally, our framework supports automatic generation of source code and platform configuration files from the abstract model, thereby accelerates the development process. Compared with existing work, our DSE techniques and the integrated tool framework advance the research results on reliability-aware design further into practice. The analysis and optimization techniques are evaluated with extensive experiments and the overall framework is applied on real-world case studies and demonstrators.